TMT4 PCIe Margin Tester

More than a new tool. An entirely new category.

TMT4 Margin Tester Overview

Industry’s first dedicated Transmit/Receive (Tx/Rx) lane margining tool, the Tektronix TMT4 allows you to easily assess the link health of your PCIe® generation 3 and 4 designs in minutes, not days. Acting as an active link partner with the device under test (DUT), the instrument can control presets via protocol and quickly display eye diagrams with their associated link training parameters, providing insights into potential design flaws on a lane-by-lane or preset-by-preset basis.
PCIE® and PCI Express® are registered trademarks and/or service marks of PCI-SIG.

Fast, Easy PCIe Lane Margining

The TMT4 Margin Tester complements existing Bit Error Rate Tester (BERT) and oscilloscope solutions for margin testing. Unlike BERT and oscilloscope systems, the TMT4 Margin Tester’s simple setup, configuration, and user interface minimizes the need for senior engineers to ensure systems are set up properly for testing, and enables a broader team of users to quickly assess the health of the link formed between Margin Tester and their DUT. Its targeted Tx/Rx capability allows you to capture issues with PCIe Gen 3 and Gen 4 communications on both ends of the link and enables teams to evaluate the link health of up to x16 Gen 4 links, across all PCIe presets 0-9, in minutes.

Simple Setup, Fast Results

With the TMT4 Margin Tester link health evaluation takes as little as two minutes.

The DUT Tx test provides 2 key pieces of data: eye diagrams for each lane-preset combination measured at the receiver of the Margin Tester and the associated receiver training values the Margin Tester used to open the eye that is displayed.
The DUT Rx test is a functional evaluation of the DUT’s receiver path. The test aims to determine how far the transmitted signal amplitude from the Margin Tester can be decreased, within an expected range of operation, before errors are returned.

A Full Suite of PCIe Adapters and Cables

The TMT4 Margin Tester supports most common PCIe form factors by means of 11 adapters available for CEM, M.2, U.2, and U.3. A single 16-lane ribbon cable with high density PCIe connectors connects the Margin Tester to any of the adapters, except for the M.2 edge adapter, which has its own integrated cable to accommodate different insertion loss specifications.